Thin film transistors (TFTs) are used in a liquid crystal display (LCD) as switching elements for pixel units. Currently, a bottom gate TFT structure as shown in FIG. 1 is generally employed by most of the manufacturers of TFT-LCDs. The structure mainly comprises the following layers: a glass substrate 100 and a gate 200, a gate insulating layer 300, a semiconductor layer 400, a doped semiconductor layer 500, source and drain electrodes 700, a passivation layer 800, and a pixel electrode 900, which are formed on the glass substrate 100 in order from the bottom. The manufacturing processes of the bottom gate TFT are outlined as follows:
1. A metal thin film is deposited on a substrate (e.g., a glass or a single crystal silicon wafer) by magnetic sputtering, and then a pattern of a gate line and a gate electrode is formed by photolithography and etching. Conventionally, the target material for depositing the metal thin film normally comprises Al and Al alloy, and other metals and alloys may also be used when an integrated circuit (IC) is prepared.
2. A SiNx or SiOxNy thin film layer is prepared by chemical vapor deposition (CVD) as a gate insulating layer. The semiconductor layer (e.g., an a-Si layer) and the doped semiconductor layer (e.g., an N+ a-Si layer) are deposited in a same process on the gate insulating layer by CVD. The semiconductor layer and the doped layer are patterned to form a silicon island and a channel region by photolithography and dry etching.
3. A metal layer is deposited on the doped semiconductor layer by magnetic sputtering, and source and drain electrodes and a data line are formed by photolithography and etching. The materials for the source and drain electrodes and the date line comprise metals of high melting temperature, such as Mo, Cr, Ti, or MoW, or alloys thereof, and the formed source and drain electrodes are in good ohmic contact with the doped semiconductor layer, respectively.
4. A passivation layer (e.g., a SiOxNy layer) is deposited by CVD and thus a channel protection layer is prepared by photolithography and etching, and a via hole is etched in the protection layer simultaneously.
5. A pixel electrode layer (e.g., an ITO conductive thin film) is deposited by magnetic sputtering, a pixel electrode pattern is formed by photolithography and etching, and the pixel electrode is connected with, for example, the drain electrode, through the via hole.
The TFT structure formed through the above processes is of the follow features: the structure is simple and is relatively easy to be manufactured; the processes used for forming each layer are relatively simple; and the yield is relatively high. For example, it is possible to use a 6mask process, a 5mask process, a 4mask process and even a 3mask process (in the processes, one mask corresponds to one photolithography and etching) to perform the formation and the required equipments are not needed to be changed.
However, as the market for TFT-LCD televisions is expanding and the generation of the production line has been advanced, the size of a panel is becoming lager and lager. The requirements for the panels with relatively larger size and used in a television are different from those for the panels with relatively small size and used in a computer monitor. Increase of the size of a panel requires increase of the length of the gate lines and the data lines, and the total resistance of the lines increases, which results in retardation of signal and therefore causes the problems such as cross-talk and non-uniform brightness in the horizontal direction.
For the panels with a larger size and used in a television, the materials currently used for the source and drain electrodes to substitute the high resistance refractory metals, such as Mo, Cr, and alloys thereof comprise Al or Al alloy. However, since the contact between an Al layer and a N+ doping semiconductor layer is not good due to the large difference in work functions, a thin Mo layer is firstly deposited as a buffer layer on an underlying layer. In addition, in order to resolve the problem of the poor contact between the pixel electrode and the Al layer, a thin Mo layer is deposited on the Al layer. With above configuration, not only the problem of large contact resistance of the Al layer with the ITO thin film but also the problem that hillocks are generated when pure Al is heated is resolved. However, the following disadvantages accompany the above advantages when such sandwich structure is employed.
1. The problems with respect to etching occur, for example, the source and drain electrodes are prone to break, the reason of which is a difference between etching rates of the intermediate Al layer and the underlying and overlying Mo metal layers.
2. The productivity is decreased, because three layers of two kinds of metals are needed to be deposited, which increases the deposition period compared with depositing only one kind of metal.
3. The cost is increased, because the current market price of Mo is greatly higher than that of Al.